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Data Sheet
CURRENT CHANNEL ADCS
Figure 39 shows the ADC signal path and signal processing for
Current Channel A, which is accessed through the IAP and IAN
pins. The signal path for Current Channel B is identical and is
accessed through the IBP and IBN pins. The ADC output is a
twos complement, 24-bit data-word that is available at a rate of
6.99 kSPS (thousand samples per second). With the specified full-
scale analog input of ±250 mV and a PGA_Ix gain setting of 2,
the ADC produces its maximum output code. The ADC output
swings between ?6,500,000 LSBs (decimal) and +6,500,000 LSBs.
This output varies from part to part. The signal path includes a
xIGAIN register to modify the current gain for Current
Channel A or Current Channel B. This register can be used to
match Current Channel B to Current Channel A for simple
calibration and computation. This gain is performed using the
BIGAIN register (Address 0x28C and Address 0x38C). The
Current Channel A gain can be modified with the AIGAIN
register (Address 0x280 and Address 0x380).
As shown in Figure 39, there is a high-pass filter (HPF) in each
current channel signal path. The HPF is enabled by default and
removes any dc offset in the ADC output. It is highly recom-
mended that this filter be enabled at all times, but it can be
disabled by clearing the HPFEN bit (Bit 2) in the CONFIG
register (Address 0x102). Clearing the HPFEN bit disables the
filters in both current channels and in the voltage channel.
di/dt Current Sensor and Digital Integrator
As shown in Figure 39, the current channel signal path for both
Channel A and Channel B includes an internal digital integrator.
This integrator is disabled by default and is required only when
interfacing with a di/dt sensor, such as a Rogowski coil. When
using either a shunt resistor or a current transformer (CT), this
integrator is not required and should remain disabled.
A di/dt sensor detects changes in the magnetic field caused by
ac current. Figure 40 shows the principle of a di/dt current
sensor.
MAGNETIC FIELD CREATED BY CURRENT
(DIRECTLY PROPORTIONAL TO CURRENT)
+ EMF (ELECTROMOTIVE FORCE)
– INDUCED BY CHANGES IN
MAGNETIC FLUX DENSITY (di/dt)
ADE7953
The flux density of a magnetic field induced by a current is
directly proportional to the magnitude of the current. Changes
in the magnetic flux density passing through a conductor loop
generate an electromotive force (EMF) between the two ends of
the loop. The EMF is a voltage signal that is proportional to the
differential of the current over time (di/dt). The voltage output
from the di/dt sensor is determined by the mutual inductance
between the current-carrying conductor and the di/dt sensor.
The current signal must be recovered from the di/dt signal
before it can be used. An integrator is therefore necessary to
restore the signal to its original form.
The ADE7953 has a built-in digital integrator on each current
channel that recovers the current signal from the di/dt sensor.
Both digital integrators are disabled by default. The digital
integrator on Current Channel A is enabled by setting the
INTENA bit (Bit 0) in the CONFIG register (Address 0x102).
The digital integrator on Current Channel B is enabled by setting
the INTENB bit (Bit 1) in the CONFIG register (Address 0x102).
VOLTAGE CHANNEL ADC
Figure 41 shows the ADC signal path and signal processing for
the voltage channel input, which is accessed through the VP and
VN pins. The ADC output is a twos complement, 24-bit data-
word that is available at a rate of 6.99 kSPS (thousand samples
per second). With the specified full-scale analog input of ±500 mV
and a PGA_V gain setting of 1, the ADC produces its maximum
output code. The ADC output swings between ?6,500,000 LSBs
(decimal) and +6,500,000 LSBs. Note that this output varies
from part to part. The signal path includes a xVGAIN register
to modify the voltage gains for the voltage channel. AVGAIN
(Address 0x281 and Address 0x381) is the primary voltage gain
register used, affecting RMS and Channel A energy register
readings. Most frequently, the energy gain registers, not the
voltage gain registers, are used in calibration. In the unique case
that both the AVGAIN register and Current Channel B are
used, set BVGAIN (Address 0x28D and Address 0x38D) to the
same AVGAIN value to ensure equal gain in both channels.
As shown in Figure 41, there is a high-pass filter (HPF) in the
voltage channel signal path. The HPF is enabled by default and
removes any dc offset in the ADC output. It is highly recom-
mended that this filter be enabled at all times, but it can be
disabled by clearing the HPFEN bit (Bit 2) in the CONFIG
register (Address 0x102). Clearing the HPFEN bit disables the
filters in both current channels and in the voltage channel.
Figure 40. Principle of a di/dt Current Sensor
Rev. B | Page 21 of 72
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